Yield enhancement designs for WSI cube connected cycles

Abstract

Yield enhancement designs for wafer-scale cube-connected cycles (CCCs) are presented and analyzed. Improvements in yield can be achieved through silicon area reduction and/or through the incorporation of defect/fault tolerance in the architecture. Consequently, a compact layout strategy is proposed for CCCs. An implementation of wafer-scale CCCs based on a universal building block is presented. This implementation facilitates the introduction of redundancy to achieve direct-tolerance. Expressions for the yield of various yield enhancement designs are derived and compared numerically for several sizes of wafer-scale CCCs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>