Performance modeling of analog integrated circuits using least-squares support vector machines

Abstract

This paper describes the application of Least-Squares Support Vector Machine (LS-SVM) training to analog cir-cuit performance modeling as needed for accelerated or hi-erarchical analog circuit synthesis. The training is a type of regression, where a function of a special form is fit to experimental performance data derived from analog cir-cuit simulations. The method is contrasted with a feasi-bility model approach based on the more traditional use of SVMs, namely classification. A Design of Experiments (DOE) strategy is reviewed which forms the basis of an ef-ficient simulation sampling scheme. The results of our func-tional regression are then compared to two other DOE-based fitting schemes: a simple linear least-squares regres-sion and a regression using posynomial models. The LS-SVM fitting has advantages over these approaches in terms of accuracy of fit to measured data, prediction of intermedi-ate data points and reduction of free model tuning parame-ters. 1.