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An integrated, CMOS, constant-fraction timing discriminator for multichannel detector systems
41
Citations
2
References
1995
Year
EngineeringAnalog-to-digital ConverterConstant-fraction Timing DiscriminatorMixed-signal Integrated CircuitAnalog DesignTiming AnalysisMulti-rate Signal ProcessingComputer EngineeringTime WalkIntegrated CircuitsDigital Circuit DesignMicroelectronicsSignal ProcessingMultichannel Detector Systems
An integrated, CMOS, constant-fraction timing discriminator (CFD) designed to accommodate the special requirements of large, multichannel detector systems is described. This CFD features on-chip, zero-crossing shaping and an automatic walk setting to limit the number of user adjustments. The circuit is realized in the Orbit 1.2 micron, N-well, CMOS process and operates with a 5 V power supply. The time walk in a 100:1 dynamic range (-15 mV to -1.5 V) is less than /spl plusmn/250 ps for a 10 ns rise time/10 ns fall time signal, yet the power dissipation is about 2 mW/channel. The discriminator has a 170 micron pitch, is 800 microns long, and is structured for arraying multiple channels on a single die.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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