SLIDER: Simulation of Layout-Injected Defects for Electrical Responses

Abstract

Logic-level simulation has been the de facto method for simulating defect/faulty behavior for various testing tasks since it offers a good tradeoff between accuracy and speed. Unfortunately, by abstracting defect behavior to the logic level (i.e., a fault model), it also discards important information that inevitably results in inaccuracies. This paper describes a fast and accurate defect simulation framework called SLIDER (simulation of layout-injected defects for electrical responses). SLIDER uses well-developed mixed-signal simulation technology that is conventionally used for design verification. There are three innovative aspects that distinguish SLIDER from prior work in this area: 1) accuracy resulting from defect injection taking place at the layout level; 2) speedup resulting from careful and automatic partitioning of the circuit into maximal digital and minimal analog domains for mixed-signal simulation; and 3) complete automation that includes defect generation, defect injection, design partitioning, netlist extraction, mixed-signal simulation, and test-data extraction. The virtual failure data created by SLIDER is useful in a variety of settings that include diagnosis resolution improvement, defect localization, fault model evaluation, and evaluation of yield/test learning techniques that are based on failure data analysis.