An efficient test method for embedded multi-port RAM with BIST circuitry

Abstract

The read/write disturb test is as indispensable for multi-port RAM testing as the functional memory test. This due to the need to check the influence of both a write operation under the read condition and a concurrent read operation upon the same memory cell through different ports. This paper describes novel algorithmic test patterns that are suitable for embedded multi-port RAM with BIST (built-in self-test) circuitry that realizes, for all ports, the functional memory test and the read/write disturb test concurrently while enabling memory operation. It is shown that these patterns can also detect BIST malfunctions even though they have about the same pattern length as the standard functional test patterns for single-port RAMs.