A high-efficiency thin-film SOI power MOSFET having a self-aligned offset gate structure for multi-gigahertz applications

Abstract

A highly efficient radio-frequency (RF) thin-film SOI power MOSFET having a self-aligned offset gate structure has been fabricated, It was fabricated using a self-aligned offset gate structure based on a lightly doped drain (LDD) structure to reduce the on-resistance and thus increase the power-added efficiency. The target breakdown voltage was 10 V, and the fabricated device had a breakdown voltage of 14.3 V. The on-resistance of a thin-film SOI power MOSFET using titanium salicide process was lower than that of the one fabricated using a tungsten polycide process. The cutoff frequency and maximum oscillation frequency of the titanium salicide process were 17 and 24 GHz, respectively. Its power-added efficiency at 2 GHz was 67% and its saturation output power was 20 dBm when the drain supply voltage was 3.0 V. Its power-added efficiency at 5.8 GHz was 53% and its saturation output power was 19 dBm when the drain supply voltage was 3.0 V. The dc and RF performances of the power MOSFET fabricated using the titanium salicide process were better than those of the one fabricated using the tungsten polycide process.