Placement of 3D ICs with thermal and interlayer via considerations

TLDR

Thermal issues and interlayer via density constraints are key design limits for three‑dimensional integrated circuits that must be addressed during placement. The study develops analytical and partitioning‑based techniques to explore the trade‑off between wirelength, interlayer via counts, and thermal effects. These techniques partition the design space and analytically model wirelength, via density, and thermal impact to guide placement decisions. The method achieves wirelengths within 2 % of optimal while reducing interlayer via counts by 46 %, and cuts temperatures by about 20 % with only a 1 % increase in wirelength and a 10 % increase in via counts.

Abstract

Thermal problems and limitations on interlayer via densities are important design constraints on three-dimensional integrated circuits (3D ICs), and need to be considered during global and detailed placement. Analytical and partitioning-based techniques are developed to explore the tradeoff between wirelength, interlayer via counts, and thermal effects. This method allows wirelengths to be minimized for any desired interlayer via density and temperatures to be reduced while minimizing deleterious effects on wirelength and interlayer via counts. Wirelength reductions within 2% of the optimal can be achieved using 46% fewer interlayer vias. Temperatures can be reduced by about 20% with only 1% higher wirelengths and 10% more interlayer vias.