TSV manufacturing yield and hidden costs for 3D IC integration

TLDR

3D integration encompasses packaging, IC integration, and silicon integration, with TSV technology used in IC and silicon integration but not in packaging. The study aims to evaluate TSV manufacturing yield and hidden costs while outlining a 3D integration roadmap. The authors analyze TSV, a technology over 26 years old, in the context of a dual‑active‑surface concept for 3D integration.

Abstract

3D integration consists of 3D IC packaging, 3D IC integration, and 3D Si integration. They are different and in general, the TSV (through-silicon-via) separates the 3D IC packaging and 3D IC/Si integrations, i.e., the latter two use TSV, but 3D IC packaging does not. TSV for 3D integration is >26 years old technology, which (with a new concept that every chip could have two active surfaces) is the focus of this study. Emphasis is placed on the TSV manufacturing yield and hidden costs. A 3D integration roadmap is also provided.