An asynchronous dataflow FPGA architecture

TLDR

The paper presents a high‑performance FPGA architecture designed to efficiently prototype asynchronous, clock‑less logic. The architecture implements low‑level application logic as token‑based asynchronous dataflow functions, realized with finely pipelined asynchronous circuits that achieve high computation rates and support designs operating up to 400 MHz in a TSMC 0.25 µm CMOS process. The resulting FPGA architecture preserves the performance advantages of custom asynchronous designs while enabling post‑fabrication logic reconfigurability.

Abstract

We discuss the design of a high-performance field programmable gate array (FPGA) architecture that efficiently prototypes asynchronous (clockless) logic. In this FPGA architecture, low-level application logic is described using asynchronous dataflow functions that obey a token-based compute model. We implement these dataflow functions using finely pipelined asynchronous circuits that achieve high computation rates. This asynchronous dataflow FPGA architecture maintains most of the performance benefits of a custom asynchronous design, while also providing postfabrication logic reconfigurability. We report results for two asynchronous dataflow FPGA designs that operate at up to 400 MHz in a typical TSMC 0.25 /spl mu/m CMOS process.