Automatic functional test generation using the extended finite state machine model

Abstract

We present a method of automatic generation of functional vectors for sequential circuits. A high-level description of the circuit, in VHDL or C, is assumed available. Our method automatically transforms the high-level description, in VHDL or C, of a circuit into an extended finite state machine (EFSM) model using which functional vectors are generated. The EFSM model is a generalization of the traditional state machine model. It can be considered as a compact representation of the machine that preserves many nice properties of a traditional state machine. Theoretical background of the EFSM model will be addressed. Our method guarantees that the generated vectors cover every statement in the high-level description at least once. Experimental results show that a set of comprehensive functional vectors for sequential circuits with more than a hundred flip-flops can be generated automatically in a few minutes of CPU time using our prototype system.