A Fully Integrated 0.13 $\mu{\hbox {m}}$ CMOS Low-IF DBS Satellite Tuner Using Automatic Signal-Path Gain and Bandwidth Calibration

Abstract

This paper presents the first low-IF fully integrated receiver for DBS satellite TV applications realized in 0.13 mum CMOS. A wideband ring oscillator based frequency synthesizer having a large frequency step was used to downconvert a cluster of channels to a coarsely defined low-IF frequency, while the second downconversion to baseband was performed in the digital domain. Eliminating the oscillator inductors reduced the parasitic magnetic coupling from the digital core, allowing a single-chip integration of the sensitive tuner and the noisy digital demodulator. A significant die area reduction was achieved by using a single oscillator to cover the entire satellite TV spectrum, while a noise attenuator was cascaded with the PLL loop filter to reduce the equivalent tuning gain. The low-IF architecture allowed a discrete-step AGC that improves both tuner noise and linearity performance. Tuner gain and IF corner frequency were calibrated using replica ring oscillators that are tuned up to the onset of oscillations. The tuner specifications include: 90 dB gain range, 9 dB noise figure at max gain, +25 dBm IIP3 at min gain, 1.3degrms integrated phase noise, les50 dBc spurs, 0.7 W power consumption from dual 1.8/3.3-V supplies, and 1.8times1.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die area