Publication | Closed Access
Formal Semantics of Synchronous SystemC
44
Citations
14
References
2003
Year
Formal SemanticsSystemc Delta DelayFormal SpecificationEngineeringVerificationFormal MethodsComputer ArchitectureComputer EngineeringSystems EngineeringSynchronous Hdl SubsetsSynchronous SubsetComputer ScienceHardware Description LanguageFormal TechniqueParallel ComputingTimed SystemFormal VerificationSystem Specification
In this article, a denotational definition of a synchronous subset of SystemC is proposed. The subset treated includes modules, processes, threads, wait statement, ports and signals. We propose a formal model for SystemC delta delay. Also, we give a complete semantic definition for the language's two-phase scheduler. The proposed semantic can constitute a base for validating the equivalence of synchronous HDL subsets.
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