A physically based analytic model of FET Class-E power amplifiers-designing for maximum PAE

Abstract

In this paper, we present a new Class-E power-amplifier model. Through a physically based analysis, our novel approach yields closed-form expressions for input, output, and dc power. These expressions yield the important figures-of-merit [gain, drain efficiency, and power-added efficiency (PAE)]. Using standard device parameters, design optimization for maximum PAE follows directly from the analysis and applies to bath integrated and discrete transistor implementations. For integrated designs, the optimal FET aspect ratio can be determined, given the design variables of the Class-E output network (output power, frequency, supply voltage, and loaded-Q of the output resonator). In a discrete transistor application, the Class-E network can be optimized for one of the design variables. The detrimental effects of the device parasitics on the amplifier's performance at UHF and microwave frequencies are accounted for in the model and explained in this paper. We verified the validity of the model by comparing our computed values against those from simulations using an optimized 0.5-/spl mu/m CMOS level-3 SPICE model.