NMOS IC's for clock and data regeneration in gigabit-per-second optical-fiber receivers

Abstract

The design and performance of two essential analog circuits in optical-fiber receivers is described. A time-interleaved decision circuit is capable of regenerating 35-mV nonreturn-to-zero (NRZ) data inputs to full logic levels at 1.1 Gb/s with 10/sup -11/ bit error rate (BER), and a phase-locked loop (PLL) extracts the clock from a 2/sup 23/ long pseudorandom sequence at 1.5 Gb/s with 13-ps r.m.s. jitter. The two circuits have been implemented as 1- mu m NMOS ICs, and in their core area dissipate 200 and 350 mW, respectively.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>