A 155-MHz clock recovery delay- and phase-locked loop

Abstract

The authors describe a completely monolithic delay-locked loop (DLL) that may be used either by itself as a deskewing element, or in conjunction with an external voltage-controlled crystal oscillator (VCXO) to form a delay- and phase-locked loop (D/PLL). By phase shifting the input data rather than the clock, the DLL and D/PLL provide jitter-peaking-free clock recovery. Additionally, the jitter transfer function of the D/PLL has a low bandwidth for good jitter filtering without compromising acquisition speed. The D/PLL described here exhibits less than 1 degrees r.m.s. jitter on the recovered clock, independent of the input data density. No jitter peaking is observed over the 40-kHz jitter bandwidth.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>