Design and analysis of high-speed random access memory with Coulomb blockade charge confinement

Abstract

A silicon-based memory cell utilizing Coulomb blockade is analyzed for use as a high-speed RAM. Operation principles and design guidelines are given by simple analytical modeling and simulations. By performing transient waveform Monte Carlo simulations, high-speed write operation is demonstrated with a time shorter than 10 ns. The memory node voltage of less than 0.1 V is detected by a newly proposed split-gate cell structure with a minimum disturbance to/from nonselected cells, which indicates the compatibility of this structure with conventional field effect transistors.