Single Event Transient Suppressor for Flip-Flops

Abstract

Some single event upset (SEU)-hardened flip-flops cannot mitigate single event transients (SET) that come from the upstream combinational circuits and propagate to the data inputs of flip-flops near the capturing clock edge. This paper presents a SET suppressor that can mitigate such SETs. By adjusting the clock edge timing so that the flip-flop captures data when the data returns to a correct state, the SET suppressor protects a flip-flop against SETs. The clock edge timing adjustment results in flip-flop delay. However, the SET suppressor almost does not introduce flip-flop delay when no SET occurs near the capturing clock edge, which is a great majority of time.