Simultaneous capacitor sharing and scaling for reduced power in pipeline ADCs

Abstract

A technique for reducing power dissipation in pipeline analog-to-digital converters (ADCs) is presented. The technique stems from the observation that the amplifier of the first stage is used to charge the input capacitors of the subsequent stage. At the end of the amplification phase, the feedback capacitor of the first stage holds the residue voltage across it and can be reused in the second stage. The feedback capacitor is designed to be a network of capacitor and switches. With appropriate clocking, the network is re-configured to form the input sampling network of the second stage. This reuse is combined with scaling down of the capacitors to result in more power savings