Impact of Error Correction Code and Dynamic Memory Reconfiguration on High-Reliability/Low-Cost Server Memory

Abstract

History has shown that DRAM technology shrinks as the server memory density grows and, at the same time, user expectation of system uptime increases. Given this, new mitigation techniques are required to reduce the impact of DRAM faults on server reliability, availability, and serviceability (RAS). This study shows the trade-offs in the effectiveness of two commonly used error correction codes (ECC) and two dynamic memory reconfiguration (DMR) schemes with various types of anticipated memory failures. This study proposes a "RAS intelligent" way to look at device reliability as DRAM technology scales below 100nm