Impact of polysilicon depletion in thin oxide MOS technology

Abstract

Accurate characterization of thin oxide conduction current, breakdown, and MOSFET current require an accounting for the voltage drop due to the depletion of the polysilicon gate. The reduction of oxide thickness and polysilicon doping ascerbate this effect. Scaled n+/p+ dual gate CMOS technology incorporates both these trends, due to process integration constraints which limit the concentration of active dopants in polysilicon. The authors investigate effects of polysilicon depletion on the thin oxide MOS system.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>