An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures

Abstract

The use of cycle-accurate software simulators as a foundation for the exploration of all the possible full-system hardware-software (hw-sw) configurations does not appear to be anymore a feasible way to handle modern embedded multicore systems complexity. In this letter, an field programmable gate array (FPGA)-based cycle-accurate hardware emulation framework is presented and proposed as a research accelerator for the exploration of complete multicore systems. The framework provides the possibility to extract from the automatically instantiated hardware-emulated system a set of metrics for the assessment of the performance and the evaluation of the architectural tradeoffs, as well as the estimation of figures of power and area consumption of a prospective application-specified integrated circuit (ASIC) implementation of the considered architecture.