A 100 MHz A/D interface for PRML magnetic disk read channels

Abstract

An analog-to-digital interface IC suitable for PRML read channels with a 100 MHz output rate has been designed and fabricated in a 1.2 /spl mu/m CMOS technology. The prototype IC contains a low-pass filter, symbol-rate equalizer, analog-to-digital converter, and generates all required clocks from a single external reference clock. The filters are implemented using a switched-capacitor parallel filter architecture used to implement a 3:1 decimation filter and a 3-tap programmable equalizer.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>