Analysis and design of a wideband high efficiency CMOS outphasing amplifier

Abstract

This work presents the analysis and design of a novel transformer-based power combining network for an efficient outphasing power amplifier (PA). The proposed power combining network was implemented on PCB together with two 65nm CMOS class-E PA's. Measurements show a peak output power of more than 30dBm over a 29% bandwidth around 700MHz. The peak output power at 700MHz equals 33.9dBm. The 10dB back-off efficiency is larger than 27.3% over the same 29% bandwidth. The 6dB back-off efficiency is larger than 46.4% over this bandwidth. The drain efficiency at 650MHz is larger than 50% over a 10dB power back-off range, which is, to our best knowledge, the highest back-off efficiency reported in a CMOS outphasing PA to date.