A high-performance OC-12/OC-48 queue design prototype for input-buffered ATM switches

Abstract

This paper presents the design and prototype of an intelligent, 3-dimensional-queue (3DQ) for high-performance, scalable, input-buffered ATM switches. The 3DQ uses pointers and linked lists to organize ATM cells into multiple virtual queues according to priority, destination, and virtual connection. It enforces per-virtual connection quality-of-service (QoS) and eliminates head-of-line (HOL) blocking. Using field-programmable-gate-array (FPGA) devices, our prototype hardware can process ATM cells at 622 Mb/s (OC-12). Using more aggressive technology (multi-chip-module (MCM) and fast GaAs logic), the same 3DQ can process cells at 2.5 Gb/s (OC-48). Using the 3DQ and matrix-unit-cell-scheduler (MUCS) as essential components, an input-buffered ATM switch system has been designed, which can achieve near-100% link bandwidth utilization.