Design and implementation of a DAB channel decoder

Abstract

This paper describes the design of the de-interleaver and punctured Viterbi decoder for the Eureka-147 DAB system and their corresponding VLSI implementations. We emphasize how to efficiently handle four DAB transmission modes, time/frequency de-interleaving and path metric/survivor memory management in our development. Results show that our implementation has the characteristics of modular design, consuming less silicon area, and facilitating the extension for high transmission rate requirement. The core size of the resulting chip implementation is 4990/spl times/4930 /spl mu/m/sup 2/ based on the Taiwan Semiconductor Manufacturing Company (TSMC) 0.6 /spl mu/m single-polysilicon-triple-metal CMOS process.