A planar metallization process—Its application to tri-level aluminum interconnection

Abstract

A planar metallization process has been proposed, where contact windows or via holes of a high aspect ratio are refilled with tungsten by selective CVD enloloying WF <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</inf> . In tungsten selective CVD, an appropriate choice of substrate material and surface cleaning prior to tungsten deposition is a key factor to success. For selective deposition onto Al, Al surface is coated with MoSi <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> thin layer, and contact resistivities of refilling tungsten with n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> Si and MoSi <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> coated Al are comparable to those of conventional Al metallization. Combining a interlevel insulator surface planarization process and a planar metallization process, a tri-level aluminum interconnection process of 1 micron feature size has been constructed, which has a scheme extensive to submicron feature size.