A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS

Abstract

A 60-GHz phase-locked loop (PLL) with inductorless prescaler is fabricated in a 90-nm CMOS process. The inductor-less prescaler has a smaller chip area than previously reported ones. The PLL operates from 61 to 63 GHz and consumes 78 mW from a 1.2 V supply. The phase noise at 100 kHz and 1 MHz offset from carrier are −72 and −80 dBc/Hz, respectively. The prescaler occupies 80 × 40 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The active area of the PLL is 0.6 × 0.6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .