Design and optimization of dual-threshold circuits for low-voltage low-power applications

TLDR

Leakage power reduction is a critical issue in low‑voltage, low‑power, high‑performance systems. This work proposes using a dual‑threshold technique, assigning high‑threshold transistors to noncritical paths and low‑threshold transistors to critical paths, and develops an algorithm to optimally select high‑threshold devices under performance constraints. The authors employ a verified leakage‑current model and an optimization algorithm to determine the optimal high‑threshold assignments and estimate leakage savings. The dual‑threshold approach achieves over 80 % leakage reduction on ISCAS benchmarks, with active‑mode savings of about 50 % at low activity and 20 % at high activity, and improves standby power as well.

Abstract

Reduction in leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, we use the dual-threshold technique to reduce leakage power by assigning a high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path(s). In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high-threshold voltage. A general leakage current model which has been verified by HSPICE simulations is used to estimate leakage power. Results show that the dual-threshold technique is good for leakage power reduction during both standby and active modes. For some ISCAS benchmark circuits, the leakage power can be reduced by more than 80%. The total active power saving can be around 50% and 20% at low- and high-switching activities, respectively.