Bias-Stress Effect in Pentacene Organic Thin-Film Transistors

Abstract

The effects of bias stress in integrated pentacene organic transistors are studied and modeled for different stress conditions. It is found that the effects of bias stress can be expressed in terms of the shift in applied gate voltage ¿V for a given current. An empirical equation describing ¿V in terms of different gate and drain bias stress measurements and stress times is presented and verified. In the measured devices, ¿ <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> saturates at 14 V, independent of the gate bias-stress condition. A model based on carrier trapping rate equation that accounts for this ¿V saturation is developed. The model suggests that the ¿V saturation is due to the small density of traps compared to the channel carrier density.