Clamped inductive switching of LDMOST for smart power IC's

Abstract

This paper explores the energy capability of an integrated clamped lateral power MOS transistor. The energy capability is determined by switching the device on an inductive load. Experimental results show that the rating of the transistor in terms of energy has to be given along with the drain voltage applied during the transient regime. If the clamp voltage increases, the energy capability decreases. This is explained by the presence of a parasitic NPN transistor in the LDMOS transistor. A specific structure is designed in order to determine the energy capability that would correspond to a purely thermal failure mechanism.