A 40-to-76 GHz Balanced Distributed Doubler in 0.13-¿m CMOS Technology

Abstract

A miniature 40- to 76-GHz monolithic balanced distributed frequency doubler is developed in a commercial 0.13μm CMOS process. This balanced doubler consists of a reduced-size broadside-coupled Marchand balun and two distributed doublers, and suppresses fundamental signals better than 25 dB. The measured conversion losses are 8-11 dB for the output frequencies from 40 to 76-GHz under 6-dBm input drive, with a low dc power consumption of 12 mW. The chip size is 0.64 × 0.65 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . To the best of our knowledge, this doubler achieves the widest bandwidth among all the CMOS doublers reported to date.