Timing yield estimation from static timing analysis

TLDR

The paper proposes a method to estimate parametric timing yield and provide robust design guidance under manufacturing and operating variations. By post‑processing static timing analysis reports with a linear delay model, the approach efficiently evaluates path‑level variation effects and supports die‑to‑die and within‑die robustness strategies. Experiments on a PowerPC microprocessor demonstrate the method’s effectiveness and practical applicability.

Abstract

This paper presents a means for estimating parametric timing yield and guiding robust design for-quality in the presence of manufacturing and operating environment variations. Dual emphasis is on computational efficiency and providing meaningful robust-design guidance. Computational efficiency is achieved by basing the proposed methodology on a post-processing step applied to the report generated as a by-product of static timing analysis. Efficiency is also ensured by exploiting the fact that for small processing/environment variations, a linear model is adequate for capturing the resulting delay change. Meaningful design guidance is achieved by analyzing the timing-related influence of variations on a path-by-path basis, allowing designers perform a quality-oriented design pass focused on key paths. A coherent strategy is provided to handle both die-to-die and within-die variations. Examples from a PowerPC microprocessor illustrate the methodology and its capabilities.