IEEE Journal of Solid-State Circuits · 1993 · 31 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMicroelectronicsSemiconductor DevicesCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyIntegrated Circuit DesignLow-power Digital Circuit DesignPower ManagementPower OptimizationLow-power Cmos DesignLow-power Memory ArchitectureLow-power Memory CircuitsLow-voltage Cmos DesignPower ConsumptionPower Consumption OptimizationUltra-low-power CmosUltra-low-voltage Circuit Design
This paper describes a single-bit-line cross-point cell activation (SCPA) architecture, which has been developed to reduce active power consumption and to avoid increase in the size of high-density SRAM chips, such as 16-Mb SRAM's and beyond. A new PMOS precharging boost circuit, introduced to realize the single-bit-line structure, is also discussed. This circuit is suitable for operation under low-voltage power supply conditions. The SCPA architecture with the new word-line boost circuit is demonstrated with the experimental device, which is fabricated by a 0.4- mu m CMOS wafer process technology.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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