Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs

Abstract

This paper presents a novel formalized technique for variable tapered buffer design achieving Pareto optimal energy-delay tradeoffs. Our main focus lies on the drivers typically found in embedded SRAMs. Much work has been done for variable tapered buffer design explicitly targeting energy (and/or area) tradeoffs for a given target delay. In contrast, the formalized techniques presented here are capable of providing all existing Pareto configurations achieving optimal energy/delay tradeoffs, and this is applicable for the full range of all possible delay constraints. Based on such techniques, a transistor-level implementation is also presented to allow a discrete set of Pareto configurations (from high-speed to low-energy) to be selected at run-time. This implementation has been validated via SPICE simulations for a 65-nm CMOS technology, confirming that a very wide range in delay (more than a factor 2) and energy consumption (up to 40%) can be achieved at the SRAM level, including process variability impact effects present in CMOS nanometer technologies.