Single event latchup protection of integrated circuits

Abstract

This paper will report the test results from the development of the single event latchup protection circuitry (referred to as Space Electronics Inc.'s (SEIs) Latchup Protection Technology (LPT/sup TM/)) for several integrated circuits which are known to latchup at unacceptably low LET energies for space applications. Two devices were evaluated with LPT/sup TM/; the ADS7805 16 bit analog to digital converter and the GF10009 FPGA (Gatefield's 9000 gate flash programmable gate array).