On-Chip Voltage Down Converter to Improve SRAM Read/Write Margin and Static Power for Sub-Nano CMOS Technology

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> VDC-based dynamic power supply approach has been demonstrated to effectively improve the read margin, write margin and static power dissipation for the sub-nano SRAM design. The static power dissipation is found to be 5<formula formulatype="inline"><tex>$\times$</tex></formula> improvement in the room and high temperatures while the chip is in the standby mode. The measured data indicate the excellent <formula formulatype="inline"><tex>${\rm V}_{\rm ccmin}$</tex></formula> improvement at around 240 mV. This 2M 65 nm SRAM chip can operate at 0.7 V with the help of the on-chip VDC. Furthermore, with the programmability of the VDC, we can optimize the read margin and write margin separately to have dramatic yield improvement. In the advancement of CMOS technology, the VDC approach can improve the future SRAM cell operation without additional external power supplies and complicate design modification. </para>