Digital current mode control architecture with improved performance for DC-DC converters

Abstract

Designing a low cost, high performance digital controller is still a challenging work in the power electronics field. One of the keys to address this issue is to select the suitable digital control architecture. At present, voltage mode control architecture is widely used in the digital controller IC. But the unpredicted limit cycle due to the nonlinearity of ADC and DPWM is one of major issues in this architecture. This paper introduces a digital current mode control architecture which can well limit the oscillation amplitude, so that it can greatly reduce the design challenge for the digital controller IC by getting rid of the high resolution DPWM. Moreover, proposed adaptive ramp design can further improve system performance. Simulation and experiment results are presented to verify proposed ideas.