A New Protocol Stack Model for Network on Chip

Abstract

In this paper, we present a communication protocol for network on chip architectures which have complex packet switched communication protocols. In order to manage this complexity and advance reusability, a layered approach is taken. It is a 4-layered protocol stack including application, transaction, data-link and physical layers. Our protocol stack supports the best effort traffic as well as guaranteed bandwidth using the virtual channels which logically share the physical links. In order to evaluate the design, an HDL implementation of this protocol stack is implemented and synthesized. The results show 0.5% of a Virtex II 2VP30 FPGA is employed by our proposed protocol stack for each resource network interface