A CMOS image sensor with a simple FPN-reduction technology and a hole accumulated diode

Abstract

CMOS image sensors are generally characterized by their low power consumption, single power supply and capability for on-chip system integration in contrast with CCD image sensors. Even though CMOS image sensors have these advantages, they are not yet widely used in image capture applications because of their insufficient image quality due to the difficulty in FPN cancellation. This FPN-reduction technology and a hole accumulated diode (HAD) for sensing elements is applied to the CMOS image sensor. The CMOS image sensor consists of a 640/spl times/480 pixel array in 1/3 inch image format, a current-to-voltage converter, a correlated double sampling circuit and a timing generator. This image sensor uses a 0.35 /spl mu/m CMOS logic process with specialized add-on steps for HAD. The power supply is 3.3 V and maximum frame rate is 30 frames/s.