Hardware Implementation of Low Power, High Speed DCT/IDCT Based Digital Image Watermarking

Abstract

This paper presents a comparison with the conventional watermarking technique and the novel 5-stage pipelined implementation of DCT/IDCT which is used in digital image watermarking. The most common method of Discrete Cosine Transform (DCT)-based digital image watermarking which is used for image authentication and copyright protection is the transpose method. In this method the 2-Dimensional DCT is obtained by taking two 1-dimensional DCTs in series. The image pixel value is first divided into 8x8 blocks and the row-wise 1D DCT of each block is taken. The transpose of the blocks is then determined and a column-wise 1D DCT is ascertained which gives the 2D DCT of the data. The major advantage of this design is that, unlike the conventional DCT-based watermarking technique, this method uses a 5-stage pipeline which can bring about a speed increase of close to 500% over the conventional method which is naturally a great advantage. This technique has been tested on the standard `Lena' image. Both visible and invisible watermarking is implemented in hardware. The design is done in Verilog HDL and the simulation is done in Modelsim 6.3b. Matlab is used to produce the binary data file which is the input to the 1D DCT module. The hardware implementation is done in Xilinx XC3S4000 FPGA. The results of the comparison are discussed in the concluding sections.