An 8-bit 50+ Msamples/s pipelined A/D converter with an area and power efficient architecture

Abstract

An efficient architecture for a pipelined A/D converter is described. By sharing amplifiers along the pipeline and also completely eliminating the amplifier from the last stage, an 8-bit converter is realized using just 3 amplifiers (instead of 7 amplifiers with a conventional pipeline architecture). By using two such pipelines in parallel, a sampling rate of over 50 Msamples/s has been achieved in a 0.9-/spl mu/m CMOS technology.