2008 · 47 citations · 1 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureMemoryMicroelectronicsMemory DevicesMemory HierarchyMemory Hierarchy DesignMemory Subsystem Design3D Nand ArchitectureArea EfficiencyColumnsDie ArchitectureFlash MemoryNand Flash MemoryNand Flash Memory OrganizationNon-volatile Memory Design
We present an 8 MB/s 3-bit per cell (D3) NAND flash memory that uses the same number of ECC bytes as 2-bit per cell (D2) NAND. Since no extra columns are added in D3 devices, the 16 Gb D3 chip in this paper achieves 0.112 Gb/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> compared to 0.079 Gb/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> on D2 chips, as previously reported (K. Takeuchi et al.,2006). This is a 41% improvement in Gb/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and a 20% gain in overall die-size.
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A 70nm 16Gb 16-level-cell NAND Flash Memory
Noboru Shibata, Maejima Hiroshi, K. Isobe et al. · 2007 · 62 citations