Speed-power-accuracy tradeoff in high-speed CMOS ADCs

Abstract

In this paper the fundamental tradeoff between speed, power, and accuracy for high-speed analog-to-digital converters (ADCs) is reviewed with respect to technology scaling. The never-ending story of complementary metal-oxide-semiconductor (CMOS) technology trends toward smaller transistor dimensions has resulted to date in deep submicron transistors with lower supply voltages. Supply voltage scaling and mismatch scaling trends are discussed and it is shown that in future technologies the power consumption of matching-dominated high-speed ADCs will increase to achieve the same accuracy and speed. Also, a comparison is made between slew-rate dominated circuits and settling dominated circuits. Finally, a comparison with published high-speed ADCs is presented using the figure of merit.