Advanced verification techniques based on learning

Abstract

Article Advanced verification techniques based on learning Share on Authors: Jawahar Jain Fujitsu Laboratories of America, 77 Rio Robles, San Jose CA Fujitsu Laboratories of America, 77 Rio Robles, San Jose CAView Profile , Rajarshi Mukherjee Fujitsu Laboratories of America, 77 Rio Robles, San Jose CA and Dept. of Electrical and Computer Engineering, University of Texas at Austin, Austin TX Fujitsu Laboratories of America, 77 Rio Robles, San Jose CA and Dept. of Electrical and Computer Engineering, University of Texas at Austin, Austin TXView Profile , Masahiro Fujita Fujitsu Laboratories of America, 77 Rio Robles, San Jose CA Fujitsu Laboratories of America, 77 Rio Robles, San Jose CAView Profile Authors Info & Claims DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation ConferenceJanuary 1995 Pages 420–426https://doi.org/10.1145/217474.217564Published:01 January 1995 57citation243DownloadsMetricsTotal Citations57Total Downloads243Last 12 Months2Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

References

Page 1

	Year	Citations
Graph-Based Algorithms for Boolean Function Manipulation Bryant IEEE Transactions on Computers Circuit ComplexityComputational LogicLogic SynthesisEngineeringBoolean Function Manipulation	1986	8.8K
Dynamic variable ordering for ordered binary decision diagrams Richard Rudell International Conference on Computer Aided Design Mathematical ProgrammingCircuit ComplexityEngineeringComputer ArchitectureComputational Complexity	1993	836
SOCRATES: a highly efficient automatic test pattern generation system Michael Schulz, E. Trischler, T.M. Sarfert IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems EngineeringComputer ArchitectureTest Data GenerationSoftware EngineeringSystem-level Design	1988	568
Logic verification using binary decision diagrams in a logic synthesis environment Sharad Malik, A.R. Wang, Robert K. Brayton, Applied LogicEngineeringVerificationComputer-aided VerificationCombinational Logic Verification	2003	501
Evaluation and improvement of Boolean comparison method based on binary decision diagrams Masahiro Fujita, Hisanori Fujisawa, Nobuaki Kawato Circuit ComplexityEngineeringBoolean FunctionComparative TestComputer Architecture	2003	266
Verification of large synthesized designs Daniël Brand International Conference on Computer Aided Design Circuit ComplexityEngineeringAccelerated DesignBoolean FunctionVerification	1993	265
Recursive Learning: An attractive alternative to the decision tree for test generation in digital ci Wolfgang Kunz, Dhiraj K. Pradhan Artificial IntelligenceEngineeringTest Data GenerationSoftware EngineeringComputational Complexity	2005	161
Heuristic minimization of BDDs using don't cares Thomas R. Shiple, Ramin Hojati, Alberto Sangiovanni‐Vincentelli,	1994	100
Sequential logic optimization by redundancy addition and removal Luis Entrena, Kwang‐Ting Cheng International Conference on Computer Aided Design Mathematical ProgrammingEngineeringVlsi DesignSequential Redundancy RemovalComputer Architecture	1993	82
Tautology checking using cross-controllability and cross-observability relations E. Cerny, Christophe Mauras Circuit ComplexityCross-observability RelationsParaconsistent LogicEngineeringVerification	2002	35

Page 1