2008 · 78 citations · 40 references
EngineeringComputer EngineeringComputer ScienceDesign AutomationMicroelectronicsSystem-on-chip DesignBuilt-in Self-testDesign For TestabilityIntegrated Circuit DesignInterconnect DesignPhysical DesignVery-large-scale Integration LayoutElectrical TestabilityInteger Linear ProgrammingInterconnect OptimizationLinear Integer OptimizationTechnology ScalingTest Access Mechanism DesignTest OptimizationThrough-silicon Vias
Test-access mechanisms (TAMs) and test wrappers (e.g., the IEEE Standard 1500 wrapper) facilitate the modular testing of embedded cores in a core-based system-on-chip (SOC). Such a modular testing approach can also be used for emerging three-dimensional integrated circuits based on through-silicon vias (TSVs). Core-based SOCs based on 3D IC technology are being advocated as a means to continue technology scaling and overcome interconnect-related bottlenecks. We present an optimization technique for minimizing the test time for 3D core-based SOCs under constraints on the number of TSVs and the TAM bitwidth. The proposed optimization method is based on a combination of integer linear programming, LP-relaxation, and randomized rounding. Simulation results are presented for the ITC 02 SOC Test Benchmarks and the test times are compared to that obtained when methods developed earlier for two-dimensional ICs are applied to 3D ICs.
40
Demystifying 3D ICs: The Pros and Cons of Going Vertical
W. Rhett Davis, John Wilson, Stephen Mick et al. · IEEE Design & Test of Computers · 2005 · 832 citations
Engineering, Computer Engineering, Electrical Engineering +17
A thermal-driven floorplanning algorithm for 3D ICs