A 167-Processor Computational Platform in 65 nm CMOS

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A 167-processor computational platform consists of an array of simple programmable processors capable of per-processor dynamic supply voltage and clock frequency scaling, three algorithm-specific processors, and three 16 KB shared memories; and is implemented in 65 nm CMOS. All processors and shared memories are clocked by local fully independent, dynamically haltable, digitally-programmable oscillators and are interconnected by a configurable circuit-switched network which supports long-distance communication. Programmable processors occupy 0.17<formula formulatype="inline"><tex Notation="TeX">$\ \hbox{mm}^{2}$</tex></formula> and operate at a maximum clock frequency of 1.2 GHz at 1.3 V. At 1.2 V, they operate at 1.07 GHz and consume 47.5<formula formulatype="inline"><tex Notation="TeX">$~$</tex></formula>mW when 100% active, resulting in an energy dissipation of 44 pJ per operation. At 0.675 V, they operate at 66 MHz and consume 608<formula formulatype="inline"><tex Notation="TeX">$\ \mu\hbox{W}$</tex></formula> when 100% active, resulting in a total energy dissipation of 9.2 pJ per ALU or MAC operation. </para>