A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS

Abstract

We propose a new architecture of an all-digital PLL (ADPLL) for advanced cellular radios that is optimized for 28 nm CMOS. It is based on a wide tuning range, fine-resolution class-F DCO with only switchable metal capacitors and a phase-predictive TDC. The 8mW DCO emits −157 dBc/Hz at 20MHz offset at ∼2 GHz, while fully satisfying metal density rules. The 0.4mW TDC clocked at 40MHz achieves PVT-stabilized 6 ps resolution for −108 dBc/Hz in-band phase noise. FREF spur is ultra-low at <−94 dBc. The ADPLL supports a 2-point modulation and consumes 12mW while occupying 0.22mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , thus demonstrating both 72% power and 38% area reductions over prior records.