IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1998 · 70 citations · 14 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureField-programmable Gate ArraysReconfigurable ComputingDynamic ReconfigurationField-programmable Gate Array ArchitectureFine-grained Reconfigurable ArchitecturesFpga ArchitectureReconfigurable System ArchitectureRun-time ReconfigurationDynamic Circuit ReconfigurationField-programmable Gate Array ReconfigurationField-programmable Gate Arrays (Fpgas)Hardware ResourcesReconfigurationReconfiguration Of Field-programmable Gate ArraysTemporal LocalityTemporal Locality Exploitation
Field‑programmable gate arrays are ideal for application‑specific architectures because they allow fine‑grained specialization, and run‑time reconfiguration extends this flexibility by exploiting dynamic conditions, though it incurs additional reconfiguration time. The authors introduce a functional density metric that balances the benefits of run‑time reconfiguration against its reconfiguration costs to justify its use over conventional approaches. They apply the metric to several run‑time reconfigured applications, analyzing each to assess functional density. The metric demonstrates that run‑time reconfiguration can reduce the hardware resources required for computation in several applications.
The ability to provide flexibility and allow fine-grain circuit specialization make field programmable gate arrays (FPGA's) ideal candidates for computing elements within application-specific architectures. The benefits of gate-level specialization and reconfigurability can be extended by reconfiguring circuit resources at run-time. This technique, termed run-time reconfiguration (RTR), allows the exploitation of dynamic conditions or temporal locality within application-specific problems. For several applications, this technique has been shown to reduce the hardware resources required for computation. The use of this technique on conventional FPGA's, however, requires additional time for circuit reconfiguration. A functional density metric is introduced that balances the advantages of RTR against its associated reconfiguration costs. This metric is used to justify run-time reconfiguration against other more conventional approaches. Several run-time reconfigured applications are presented and analyzed using this approach.
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