Integrating Logic Analyzer Functionality into VHDL Designs

Abstract

We present a combined hardware and software system for the debugging of FPGA designs. It provides a powerful logic analyzer implemented as a fully parameterized VHDL description. The system can insert the analyzer into a user design without manual labor required from the user. All processing is done on the VHDL-level, facilitating vendor-independent, source-level hardware debugging. The system also allows multiple independent FPGA-systems to be debugged in a single framework.