Constructive analysis of cyclic circuits

TLDR

Traditionally, circuits with combinational loops are found only in asynchronous designs, but they can also be useful for synchronous circuit design and arise from high‑level language behavioral compiling, enabling circuit size reduction. The study proposes a symbolic algorithm to detect synchronous behavior in sequential circuits with combinational loops and generate equivalent loop‑free circuits. The algorithm is applied to hardware and software synthesis from the Esterel synchronous programming language.

Abstract

Traditionally, circuits with combinational loops are found only in asynchronous designs. However, combinational loops can also be useful for synchronous circuit design. Combinational loops can arise from high-level language behavioral compiling, and can be used to reduce circuit size. We provide a symbolic algorithm that detects if a sequential circuit with combinational loops exhibits standard synchronous behavior, and if so, produces an equivalent circuit without combinational loops. We present applications to hardware and software synthesis from the Esterel synchronous programming language.